The ability to perform and achieve high speed transmissions of digital data has become expected in today's computing environment. In most cases, the transmission of digital data over longer distances is accomplished by sending the data in a high-speed serial format (i.e., one single bit after another) over a communication link designed to handle computer communications. In this fashion, data can be transferred from one computer system to another, even if the computer systems are geographically remote.
In order for high-speed serial transmission to occur, the digital data signal from inside the computer must be transformed from the parallel format into a serial format prior to transmission of the data over the serial communication link. This transformation is generally accomplished by processing the computer's internal data signal through a piece of computer equipment known as a serial link transmitter or “serializer.” The function of the serializer is to receive a parallel data stream as input and, by manipulating the parallel data stream, output a serial form of the data capable of high-speed transmission over a suitable communication link. Once the serialized data has arrived at the desired destination, a piece of computer equipment known as a “deserializer” is employed to convert the incoming data from the serial format to a parallel format for use within the destination computer system.
For high speed serializer/deserializer (HSS) link pairs, a frequency offset can occur between the frequency of the data coming in and the reference clock. Any frequency offset between the transmitter and receiver of a link pair causes the clock-data-recovery (CDR) loop to chase the optimum sampling point with some delay. The inability to track the offset accurately increases jitter and degrades the link performance, e.g., by increasing the bit error rate.
Accordingly, a need exists for better compensation of frequency offset adjustment in a serial link transmitter/receiver pair. The present invention addresses such a need.